This core is aimed at optimizing both performance and resource usage: it is designed focusing on the memory block number reductions, while the specific functionality implemented is really eager of memory. The best resource usage vs bandwidth ratio is obtained using the IP core in conjunction with the HP-DDR2/HP-DDR3 Controller FPGA IP Core. The core is configurable through VHDL generics, in particular with respect to pixel size, image size, pixel per clock, tile dimension. Video Rotation 90 was firstly developed on Lattice ECP5 FPGA technology and therefore is immediately available on this family, but it can be easily ported not only on other Lattice FPGA families but also on FPGAs of different Vendors . The usage of a Sanitas EG DDR controller core is suggested to reach the best performance: anyway the macro can be customized to support other third-party memory controller modules.

IP core Specifications
Supported FPGA families Lattice families
Delivery formats VHDL/EDIF
Verification support Test-bench
Tool requirements (*) Diamond 3.10 or higher

*) Earlier Diamond versions should work but have not been tested


Key Features
  • High Performance Video Rotation IP Core
  • 90-degree steps
  • Frame rate conversion
  • Frame memory type: DDR2/DDR3
  • High performance throughput and bandwidth
  • Best-in-class resource usage
  • Easily configurable core
  • Availability on Lattice technology
  • Portability on other FPGA technologies


The line_buffer_rotation extracts image tiles from the full image and rotate the tiles using a local buffer. Rotated tiles are then forwarded to the frame_buffer_manager which manages a ping-pong buffer in the external SDRAM and performs two operations: – it writes the tiles into the external SDRAM reconstructing the full rotated image – it reads the rotated image from the external SDRAM and streams it to the user logic The IP core uses a complex rotation algorithm to minimize the number of Block RAMs used in the FPGA to perform the tile rotation. In order to rotate an image, or part of it, a double buffer is usually instantiated where the new frame is stored while the previous frame is being rotated.

The IP core uses a different approach which requires only a single buffer, thus reducing the required number of Block RAMs in the FPGA by a factor of 2. Moreover, using a complex Block RAM arrangement, the IP core is able to handle multiple pixels per clock cycles maintaining the same Block RAM footprint.

Resource usage and Performance

The resource usage and performance have been evaluated adopting Lattice Diamond 3.10 on a LFE5UM-85-8 device. Needed SLICES, LUTs, BRAMs and registers are listed in one table (values are rounded), while the other shows the reachable bandwidth and the needed Block RAMs in some scenarios. The requested DDR bandwidth can be reduced by increasing the BRAMs number.

Resource Utilization
1200 1660 1380 84

*) 24bit RGB – 1080p@60fps


Performance (Lattice ECP5)
Scenario Bandwidth (MB/s) BRAMs
24bit RGB – 1080p@30fps 200 44
24bit RGB – 1080p@60fps 400 84
8bit raw – 1080p@30fps 75 20
8bit raw – 1080p@60fps 150 36
8bit raw – 1080p@120fps 300 68
8bit raw – 1080p@240fps 600 132

**) condition: 16bit DDR3-800, pixel clock up to 150MHz

Core version

The current Video Rotation 90 IP core version is 2.0.


The IP core has been implemented with Diamond 3.10 design tool. It has been deeply simulated and tested on custom boards mounting ECP5 devices.

Optional modules

The HP-DDR2 or HP-DDR3 Controller IP Core developed by Sanitas EG are strongly suggested to reach the best achievable results.
Sanitas EG reserves the right to change specifications without notice