The 10G/40G UDP Subsystem is a communication core aimed at integrating embedded applications into private Ethernet networks.
The core provides an effective infrastructure to implement very high-speed communication between an FPGA and one or several network devices, providing up to 40Gbit/s transfer rate over Ethernet. It provides a standard AXI4 interface for user applications The controller implements the UDP protocol over a LAN (Local Area Network). The 40/10 Gb Ethernet Controller has assigned programmable MAC and IP addresses.
|IP core Specifications|
|Supported FPGA families||Xilinx UltraScale, UltraScale+|
|Design file formats formats||Netlist, Source Code|
|Verification support||VHDL Test-bench, optional BIST, test application|
|Tool requirements||Xilinx Vivado 2019.1 or higher|
- 10 Gbit/s or 40Gbit/s transfer rate over Ethernet
- Included PCS and PMA
- AXI4-Stream User IF
- UDP/IP protocol
- Axi4-Lite for register configuration
- Automatic ARP management
- ARP table with programmable entries number
- Supports broadcast TX/RX Ethernet and IP packets
- Programmable MAC and IP addresses
- CRC check/generation for incoming/outgoing Ethernet packets
- Configurable maximum packet length
- Optional jumbo frame support
|Resource Utilization on Xilinx KU9P (*)|
|IP Core configuration||RAMB36 Tiles||LUTs||LUTRAMs||FFs|
|10G 64-bit internal bus||6||4600||150||4900|
|40G 256-bit internal bus||9||19500||1050||12600|
_(*) Actual resource utilization depends on selected speed and timing parameters_
Product Technical Specification
The IP core implements the UDP/IP part (bolded fields) of the communication stack represented in the following table.
The IP core block diagram is shown below :
The 10/40 G UDP Sybsystem is based on a scalable architecture supporting different Ethernet protocols. A simple user interface based on the AXI4-Stream protocol transfer UDP payload data to/from the IP core. The user can select different destination IP addresses using the TDEST field. The RX path consists of a Unified Parser that can be configured to support a wide range of data path width and clock frequency. A single optimised parser handles Ethernet, IP and UDP protocols with minimal latency and resources utilisation. In addition, the parser implements user defined packet filters. In a similar way, a Unified Packet Composer encapsulates the user provided UDP payload into UDP, IP and Ethernet. The core manages ARP replies and requests autonomously with configurable expiration time of the retrieved MAC-IP address association and automatic renewing. The core integrates PCS, PMA and transceivers for Xilinx Ultrascale and Ultrascale+ devices. The PCS/PMA layer can be omitted allowing the user to interface the core to third-party PCS using standard XGMII or XLGMII interfaces.
The IP core has been tested using a Sanitas EG board , the iTPM ADFE 1.6, which mounts a Xilinx Kintex UltraScale+ KU9P device.
Sanitas EG reserves the right to change specifications without notice