Project Info
The Memory Map over Ethernet (MMoE) IP core is a Layer 4 UDP based transport system between FPGAs and a Network Devices. This core provides a "easy to use", efficient and high speed communication system.
Description
Several devices of different type can communicate through Ethernet standard interface with a Gigabit connection. The reduced impact in terms of used resources makes the core suitable for a wide range of families of low cost FPGA devices. Control protocol software library is available for Windows and Linux OS.
| Resource Utilization Example Lattice XP2™ 32-bit interface |
|||
|---|---|---|---|
| EBR | LUT | Register | Fmax(MHz) |
| 4 | 2500 | 1400 | 125 |
Key features
- High Performance Ethernet UDP PC-FPGA data link
- Bidirectional multichannel communication
- Standard UDP/IP 10/100/1000 full speed Internet Protocol
- Link speed up to 114 MByte/sec
- ARP table and Ping management
- Easy to use
- FPGA minimum impact (no processor required)
- minimum latency protocol control module
- High configurability
- FPGA Wishbone master interface
- Control protocol software library
- Reduced PC CPU occupancy
- Video transport dedicated configuration available
