uAES128

Description

Strength points of the implemented solution are the technology independence and the reduced resource occupation: the core is really compact, taking also advantage of embedded block RAMs. The following operations are supported by the IP Core:

• Key schedule generation
• Encryption
• Decryption

Multiple key expansions can be generated and stored internally, allowing the user to change the used key on the fly without executing the key expansion command. The uAES128 IP Core is a fully synchronous design and requires 45 clock cycles for a 128-bit data block. The IP Core throughput depends on the target technology reaching 823 Mbps on a VIRTEX Ultrascale implementation.

Key features

• Advanced Encryption Standard Implementation
• Encryption and Decryption features
• 128-bit key size
• Multiple keys management
• Technology Independence
• Low Resource Occupation
• Fast data rate
• 45-clock-cycle operation for 128-bit data encryption/decryption and key expansion

Architecture

The IP architecture is based on a 32-bit datapath and implements the AES Rijndael Block Cipher Algorithm. The encoding and decoding are compliant with the NIST Advanced Encryption Standard.

Core version

The current IP core version is 1.1

Performance

Maximum frequency and throughout are reported in the following table considering four different devices representative of commonly used FPGA families: Lattice ECP5, Microsemi Igloo2, Xilinx Kintex7 and Virtex Ultrascale. Data throughput is computed by taking the data block size (128 bits), dividing it by the number of cycles (45) required by the core to encrypt/decrypt the data block, and multiplying it by the maximum clock frequency(*).

(*) Both performance and resources are calculated adopting recent design tool versions: Lattice Diamond 3.7, Microsemi Libero SoC v11.8, Xilinx Vivado 2016.2

Resource usage

For the same four devices considered in the previous table the resource usage is analyzed: LUTs, registers and embedded memory blocks are detailed.

(**) These numbers include the resources used to initialize Embedded RAM

For details and quotation please contact us (info@sanitaseg.it).

Sanitas EG reserves the right to change specification without notice.