It provides a common command interface for user applications. This core is aimed at managing embedded system applications over a private Ethernet network.
The controller implements the UDP protocol over a LAN (Local Area Network). The 1 Gigabit Ethernet Controller has assigned programmable MAC and a IP addresses.

Resource Utilization Example
Lattice ECP5 32-bit interface and Max Ethernet frames 1500 bytes
EBR LUT Register Fmax(MHz)
8 1866 1088 125

Actual resource utilization depends on selected speed and timing parameters

Key features
  • 10/100/1000 Mbit/s transfer rate over Ethernet
  • Half/Full duplex
  • GMII/RGMII/MII/RMII interfaces
  • Automatic ARP management
  • ARP table with programmable entries number
  • Supports broadcast transmit/receive Ethernet and IP packets
  • Programmable MAC and IP addresses
  • Replies to ICMP echo-requests
  • CRC check/generation for incoming/outgoing Ethernet packets
  • Checksum check/generation for incoming/outgoing UDP/IP packets
  • Configurable maximum packet length
  • Optional jumbo frame support
  • Optional Multichannel transmitter interface (16-bit or 32-bit) with independent clock domain
  • UDP protocol

Technical Description

The IP core is composed by two section: receiver and transmitter .
The receiver section includes the following functional blocks: receiver, CRC checker, receiver buffer and receiver engine.
The transmitter section includes the following functional blocks: transmitter, CRC generator, transmitter buffer and transmitter engine.

The receiver section manages the incoming UDP packets. Once a new packet is detected it is stored into the receiver buffer,
while it is checked for the CRC integrity . Furthermore, while the packet is written into the receiver buffer,
the receiver engine checks several packet fields such as MAC and IP addresses, UDP port and packet length.
If all field match programmed values, the receiver engine makes the buffer content available to the user .

The transmitter section manages the outgoing UDP packets. It checks for packets to be transmitted into the transmitter buffer and
sends them to the PHY while generating the CRC packet by packet. Once one packet is completed its CRC is sent to the PHY .
Concerning the ARP management the IP core answers to the incoming ARP requests and if the IP address of the UDP packet to be sent is not
in the ARP table a request is automatically sent to get the MAC address.

The IP core also provides a multichannel user interface, with a programmable number of channels for the transmitter section.
The multichannel access to the transmitter section is managed by an arbiter with a predefined priority .

Implemented UDP/IP stack
(dark background)
HTTP Telnet FTP DNS Application Layer
TCP UDP Transport Layer
Network Interface Network Layer
Transmission Medium Physical Layer

The IP core has been tested using the demo board “ECP5 Versa Development Kit”, hosting a Lattice ECP5UM-45F device.

Deliverables and optional modules

Netlist (EDIF) is provided together with the test bench. The integration with Wishbone Bus is available as an optional module.