The 1Gbit Ethernet/UDP/IP/MAC IP core is a communication core aimed at integrating embedded applications into private Ethernet networks.It provides an effective infrastructure to implement high-speed communication between an FPGA and one or several network devices. Together with standard interfaces, it provides a common command interface for user applications. The controller implements the UDP protocol over a LAN (Local Area Network). The 1 Gigabit Ethernet Controller has assigned programmable MAC and a IP addresses. The actual UDP core is provided together with an udp_arbiter module, whose usage is strongly suggested; some optional modules are available too.

Key Features
  • 10/100/1000 Mbit/s transfer rate over Ethernet
  • Half/Full duplex
  • GMII/RGMII/MII/RMII interfaces
  • Automatic ARP management
  • ARP table with programmable entries number
  • Supports broadcast transmit/receive Ethernet and IP packets
  • Programmable MAC and IP addresses
  • Replies to ICMP echo-requests
  • CRC check/generation for incoming/outgoing Ethernet packets
  • Checksum check/generation for incoming/outgoing UDP/IP packets
  • Configurable maximum packet length
  • Optional jumbo frame support
  • Optional Multichannel transmitter interface (16-bit or 32-bit) with independent clock domain
  • UDP protocol

The IP core implements the UDP/IP part (bolded fields) of the communication stack represented in the following table.


Application Layer HTTP Telnet FTP DNS DHCP(1)
Transport Layer TCP UDP
Network Layer IGMP ICMP(2) RARP IP ARP
Link Layer Network Interface
Physical Layer Transmission Medium

Table 1 – Communication stack. (1)Only DHCP Client. (2) Only replies to ICMP echo-requests.


The block diagram depicts in blue the actual UDP core with its sub modules, and in green the arbiter module which usage is strongly suggested to better cope with the UDP macro. Additionally five violet optional modules are represented: they implement functionalities that can be added if needed; Axi connector is available free of charge.

Figure 1 – 1Gbit Ethernet/UDP/IP/MAC Block Diagram


The actual IP core is composed by two sections: receiver and transmitter . The receiver section manages the incoming UDP packets. Once a new packet is detected it is stored into the receiver buffer, checking in the meantime the CRC integrity and several useful fields (MAC and IP addresses, UDP port and packet length). If all fields match the programmed values, the receiver engine makes the buffer content available to the user. The transmitter section manages the outgoing UDP packets. It checks for packets to be transmitted into the transmitter buffer and sends them to the PHY while generating the CRC packet by packet. Once one packet is completed its CRC is sent to the PHY. The incoming ARP requests are managed by the core too. The IP core provides also a multichannel user interface, with a programmable number of channels, for the transmitter section, managed by an arbiter with a predefined priority.

Core Version

The current IP core version is 5.7.


The UDP performance with a test application is reported in the table below.

UDP payload size MByte/s
8 byte 1.6
64 byte 12
128 byte 25
256 byte 49
512 byte 97
1024 byte 112
1472 byte 114

Table 1 – UDP Performance: MB/s wrt different payload size


Resource Usage

In the following table the resource usage of an example application is provided. The core is configured on a Lattice ECP5™ with 32-bit interface and Max Ethernet frames 1500 bytes. Resources are detailed in term of LUTs, registers and embedded memory blocks. The maximum clock frequency is reported too.


EBRs LUTs FFs Fmax(MHz)
4 1866 1088 125

Actual resource utilization depends on selected speed and timing parameters.


The IP core has been tested using the demo board “ECP5 Versa Development Kit”, hosting a Lattice ECP5UM-45F device.

Deliverables and optional modules

Source Code/Netlist is provided together with the test bench and documentation.

The following optional modules are available:

  • Axi connector (free of charge)
  • DHCP Client
  • Video Stream
  • Memory Map Master

Sanitas EG reserves the right to change specifications without notice