Linear Edge Detection

Description

The IP integrates the state of the art algorithms with noise suppression and speed optimization functions. Two alternative algorithms are available, inflection midpoint and center of mass. Edge position is calculated with 8-bit precision fixed-point arithmetic achieving a resolution of 1/256 of pixel.

The IP is configurable for function and processing speed with a parallelizable edge extractor engine and with configurable memory data width. Besides depending on the selected target technology, the IP performance comes from the combination of memory bandwidth and edge detector parallel factor.

The IP comes with a shared library allowing a simple integration in both Linux and Windows operating systems.

The Linear Edge Detection IP core is available on Lattice ECP5 FPGA and can be ported on any needed technology. In particular, this core perfectly fits on the Sanitas EG SInC and INVENTAMI platforms, both based on ECP5 technology.

Sanitas EG SInC

Sanitas EG INVENTAMI

Key Features

• High resolution, up to 2048 pixel/profile
• 8, 10 or 12-bit pixel depth
• Parallelizable architecture
• On-line image rotation
• On-line background subtraction
• On-line back projection and roto-translation
• Integrated sensor interface
• Trigger and encoder synchronization input
• Programmable output strobe
• UDP/IP gigabit Ethernet IF
• CPU bus IF
• DDR3L 32/64 memory IF
• Sanitas EG SInC & INVENTAMI compatible
• Shared library for Windows and Linux OS

Architecture

The Linear Edge Detection IP is configurable with respect to performance and area optimization. Edge engine supports parallelization to increase performance without the need of increasing clock frequency. Application interface can be either Gigabit Ethernet or CPU bus. External trigger and encoder interface (RS-485, RS-422) can be selected to synchronize sensor acquisition. Intermediate elaboration stages are available for integration and testing.

Performance

Performance depends on the selected technology operative frequency, RAM bandwidth and parallel factor. RAM image buffering is requested for image rotation and background image subtraction. The implemented algorithm needs an edge vertical orientation: the rotation function allows the optimization of the image sensor acquisition speed with horizontal ROI. If rotation is not needed, the resource occupation dramatically decreases in particular wrt EBRs. Performance detailed in the following table is related to the Sanitas EG SInC and INVENTAMI HW platforms with the engine running at 150 MHz, the DDR memory at 400 MHz (16bit SiNC, 32bit INVENTAMI) and an image size of 2048×32 pixels. All the data are estimated with the background subtraction function disabled. Expected performance on faster devices, with core running at 200 MHz and DDR memory at 533 MHz, can increase more than 25%.

(1) The table reports performance in term of laser edges per second

(2) The x4 factor on the SInC and the x8 on the INVENTAMI are estimated without rotation due to bandwidth memory limitation

Resource Occupation

LUTs, registers (FF) and embedded memory blocks (EBR) are detailed for the proposed configurations. The x4 and the x8 require larger FPGA, due to the high EBR number. The target technology is Lattice ECP5.

(1) each cell reports LUTs, FFs, EBRs in this order

Sanitas EG reserves the right to change specifications without notice

Flyer version 1.2